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| 80C186EB 80C188EB AND 80L186EB 80L188EB 16-BIT HIGH-INTEGRATION EMBEDDED PROCESSORS X Y X Full Static Operation True CMOS Inputs and Outputs Y Integrated Feature Set Low-Power Static CPU Core Two Independent UARTs each with an Integral Baud Rate Generator Two 8-Bit Multiplexed I O Ports Programmable Interrupt Controller Three Programmable 16-Bit Timer Counters Clock Generator Ten Programmable Chip Selects with Integral Wait-State Generator Memory Refresh Control Unit System Level Testing Support (ONCE Mode) Direct Addressing Capability to 1 Mbyte Memory and 64 Kbyte I O Speed Versions Available (5V) 25 MHz (80C186EB25 80C188EB25) 20 MHz (80C186EB20 80C188EB20) 13 MHz (80C186EB13 80C188EB13) Available in Extended Temperature Range ( b 40 C to a 85 C) Speed Versions Available (3V) 16 MHz (80L186EB16 80L188EB16) 13 MHz (80L186EB13 80L188EB13) 8 MHz (80L186EB8 80L188EB8) Low-Power Operating Modes Idle Mode Freezes CPU Clocks but keeps Peripherals Active Powerdown Mode Freezes All Internal Clocks Supports 80C187 Numeric Coprocessor Interface (80C186EB PLCC Only) Available In 80-Pin Quad Flat Pack (QFP) 84-Pin Plastic Leaded Chip Carrier (PLCC) 80-Pin Shrink Quad Flat Pack (SQFP) Y Y Y Y Y Y The 80C186EB is a second generation CHMOS High-Integration microprocessor It has features that are new to the 80C186 family and include a STATIC CPU core an enhanced Chip Select decode unit two independent Serial Channels I O ports and the capability of Idle or Powerdown low power modes 272433 - 1 Other brands and names are the property of their respective owners Information in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or copyright for sale and use of Intel products except as provided in Intel's Terms and Conditions of Sale for such products Intel retains the right to make changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata October 1995 COPYRIGHT INTEL CORPORATION 1995 Order Number 272433-004 1 80C186EB 80C188EB and 80L186EB 80L188EB 16-Bit High-Integration Embedded Processors CONTENTS INTRODUCTION CORE ARCHITECTURE Bus Interface Unit Clock Generator 80C186EC PERIPHERAL ARCHITECTURE Interrupt Control Unit Timer Counter Unit Serial Communications Unit Chip-Select Unit I O Port Unit Refresh Control Unit Power Management Unit 80C187 Interface (80C186EB Only) ONCE Test Mode PACKAGE INFORMATION Prefix Identification Pin Descriptions 80C186EB PINOUT PACKAGE THERMAL SPECIFICATIONS ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings PAGE 4 4 4 4 5 5 5 7 7 7 7 7 7 7 8 8 8 14 22 23 23 CONTENTS Recommended Connections DC SPECIFICATIONS ICC versus Frequency and Voltage PDTMR Pin Delay Calculation AC SPECIFICATIONS AC Characteristics 80C186EB25 AC Characteristics 80C186EB20 13 AC Characteristics 80L186EB16 Relative Timings Serial Port Mode 0 Timings AC TEST CONDITIONS AC TIMING WAVEFORMS DERATING CURVES RESET BUS CYCLE WAVEFORMS EXECUTION TIMINGS INSTRUCTION SET SUMMARY ERRATA REVISION HISTORY PAGE 23 24 27 27 28 28 30 32 36 37 38 38 41 42 45 52 53 59 59 2 2 80C186EB 80C188EB 80L186EB 80L188EB 272433 - 2 NOTE Pin names in parentheses apply to the 80C188EB 80L188EB Figure 1 80C186EB 80C188EB Block Diagram 3 3 80C186EB 80C188EB 80L186EB 80L188EB cept the queue status mode has been deleted and buffer interface control has been changed to ease system design timings An independent internal bus is used to allow communication between the BIU and internal peripherals INTRODUCTION Unless specifically noted all references to the 80C186EB apply to the 80C188EB 80L186EB and 80L188EB References to pins that differ between the 80C186EB 80L186EB and the 80C188EB 80L188EB are given in parentheses The ``L'' in the part number denotes low voltage operation Physically and functionally the ``C'' and ``L'' devices are identical The 80C186EB is the first product in a new generation of low-power high-integration microprocessors It enhances the existing 186 family by offering new features and new operating modes The 80C186EB is object code compatible with the 80C186XL 80C188XL microprocessors The 80L186EB is the 3V version of the 80C186EB The 80L186EB is functionally identical to the 80C186EB embedded processor Current 80C186EB users can easily upgrade their designs to use the 80L186EB and benefit from the reduced power consumption inherent in 3V operation The feature set of the 80C186EB meets the needs of low power space critical applications Low-Power applications benefit from the static design of the CPU core and the integrated peripherals as well as low voltage operation Minimum current consumption is achieved by providing a Powerdown mode that halts operation of the device and freezes the clock circuits Peripheral design enhancements ensure that non-initialized peripherals consume little current Space critical applications benefit from the integration of commonly used system peripherals Two serial channels are provided for services such as diagnostics inter-processor communication modem interface terminal display interface and many others A flexible chip select unit simplifies memory and peripheral interfacing The interrupt unit provides sources for up to 129 external interrupts and will prioritize these interrupts with those generated from the on-chip peripherals Three general purpose timer counters and sixteen multiplexed I O port pins round out the feature set of the 80C186EB Figure 1 shows a block diagram of the 80C186EB 80C188EB The Execution Unit (EU) is an enhanced 8086 CPU core that includes dedicated hardware to speed up effective address calculations enhance execution speed for multiple-bit shift and rotate instructions and for multiply and divide instructions string move instructions that operate at full bus bandwidth ten new instruction and fully static operation The Bus Interface Unit (BIU) is the same as that found on the original 186 family products ex- CORE ARCHITECTURE Bus Interface Unit The 80C186EB core incorporates a bus controller that generates local bus control signals In addition it employs a HOLD HLDA protocol to share the local bus with other bus masters The bus controller is responsible for generating 20 bits of address read and write strobes bus cycle status information and data (for write operations) information It is also responsible for reading data off the local bus during a read operation A READY input pin is provided to extend a bus cycle beyond the minimum four states (clocks) The local bus controller also generates two control signals (DEN and DT R) when interfacing to external transceiver chips (Both DEN and DT R are available on the PLCC devices only DEN is available on the QFP and SQFP devices ) This capability allows the addition of transceivers for simple buffering of the multiplexed address data bus Clock Generator The processor provides an on-chip clock generator for both internal and external clock generation The clock generator features a crystal oscillator a divideby-two counter and two low-power operating modes The oscillator circuit is designed to be used with either a parallel resonant fundamental or third-overtone mode crystal network Alternatively the oscillator circuit may be driven from an external clock source Figure 2 shows the various operating modes of the oscillator circuit The crystal or clock frequency chosen must be twice the required processor operating frequency due to the internal divide-by-two counter This counter is used to drive all internal phase clocks and the external CLKOUT signal CLKOUT is a 50% duty cycle processor clock and can be used to drive other system components All AC timings are referenced to CLKOUT 4 4 80C186EB 80C188EB 80L186EB 80L188EB 272433 - 4 272433 - 3 (A) Crystal Connection NOTE The L1C1 network is only required when using a thirdovertone crystal (B) Clock Connection Figure 2 Clock Configurations The following parameters are recommended when choosing a crystal Temperature Range Application Specific ESR (Equivalent Series Resistance) 40X max C0 (Shunt Capacitance of Crystal) 7 0 pF max CL (Load Capacitance) 20 pF g 2 pF Drive Level 1 mW max Figure 3 provides a list of the registers associated with the PCB The Register Bit Summary at the end of this specification individually lists all of the registers and identifies each of their programming attributes Interrupt Control Unit The 80C186EB can receive interrupts from a number of sources both internal and external The interrupt control unit serves to merge these requests on a priority basis for individual service by the CPU Each interrupt source can be independently masked by the Interrupt Control Unit (ICU) or all interrupts can be globally masked by the CPU Internal interrupt sources include the Timers and Serial channel 0 External interrupt sources come from the five input pins INT4 0 The NMI interrupt pin is not controlled by the ICU and is passed directly to the CPU Although the Timer and Serial channel each have only one request input to the ICU separate vector types are generated to service individual interrupts within the Timer and Serial channel units 80C186EB PERIPHERAL ARCHITECTURE The 80C186EB has integrated several common system peripherals with a CPU core to create a compact yet powerful system The integrated peripherals are designed to be flexible and provide logical interconnections between supporting units (e g the interrupt control unit supports interrupt requests from the timer counters or serial channels) The list of integrated peripherals includes 7-Input Interrupt Control Unit 3-Channel Timer Counter Unit 2-Channel Serial Communications Unit 10-Output Chip-Select Unit I O Port Unit Refresh Control Unit Power Management Unit Timer Counter Unit The 80C186EB Timer Counter Unit (TCU) provides three 16-bit programmable timers Two of these are highly flexible and are connected to external pins for control or clocking A third timer is not connected to any external pins and can only be clocked internally However it can be used to clock the other two timer channels The TCU can be used to count external events time external events generate non-repetitive waveforms generate timed interrupts etc The registers associated with each integrated periheral are contained within a 128 x 16 register file called the Peripheral Control Block (PCB) The PCB can be located in either memory or I O space on any 256 Byte address boundary 5 5 80C186EB 80C188EB 80L186EB 80L188EB PCB Offset 00H 02H 04H 06H 08H 0AH 0CH 0EH 10H 12H 14H 16H 18H 1AH 1CH 1EH 20H 22H 24H 26H 28H 2AH 2CH 2EH 30H Function Reserved End Of Interrupt Poll Poll Status Interrupt Mask Priority Mask In-Service Interrupt Request Interrupt Status Timer Control Serial Control INT4 Control INT0 Control INT1 Control INT2 Control INT3 Control Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Timer0 Count PCB Offset 40H 42H 44H 46H 48H 4AH 4CH 4EH 50H 52H 54H 56H 58H 5AH 5CH 5EH 60H 62H 64H 66H 68H 6AH 6CH 6EH 70H 72H 74H 76H 78H 7AH 7CH 7EH Function Timer2 Count Timer2 Compare Reserved Timer2 Control Reserved Reserved Reserved Reserved Port 1 Direction Port 1 Pin Port 1 Control Port 1 Latch Port 2 Direction Port 2 Pin Port 2 Control Port 2 Latch Serial0 Baud Serial0 Count Serial0 Control Serial0 Status Serial0 RBUF Serial0 TBUF Reserved Reserved Serial1 Baud Serial1 Count Serial1 Control Serial1 Status Serial1 RBUF Serial1 TBUF Reserved Reserved PCB Offset 80H 82H 84H 86H 88H 8AH 8CH 8EH 90H 92H 94H 96H 98H 9AH 9CH 9EH A0H A2H A4H A6H A8H AAH ACH AEH B0H B2H B4H B6H B8H BAH BCH BEH Function GCS0 Start GCS0 Stop GCS1 Start GCS1 Stop GCS2 Start GCS2 Stop GCS3 Start GCS3 Stop GCS4 Start GCS4 Stop GCS5 Start GCS5 Stop GCS6 Start GCS6 Stop GCS7 Start GCS7 Stop LCS Start LCS Stop UCS Start UCS Stop Relocation Reserved Reserved Reserved Refresh Base Refresh Time Refresh Control Reserved Power Control Reserved Step ID Reserved PCB Offset C0H C2H C4H C6H C8H CAH CCH CEH D0H D2H D4H D6H D8H DAH DCH DEH E0H E2H E4H E6H E8H EAH ECH EEH F0H F2H F4H F6H F8H FAH FCH FEH Function Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 32H Timer0 Compare A 34H Timer0 Compare B 36H 38H Timer0 Control Timer1 Count 3AH Timer1 Compare A 3CH Timer1 Compare B 3EH Timer1 Control Figure 3 Peripheral Control Block Registers 6 6 80C186EB 80C188EB 80L186EB 80L188EB A 12-bit address generator is maintained by the RCU and is presented on the A12 1 address lines during the refresh bus cycle Address bits A19 13 are programmable to allow the refresh address block to be located on any 8 Kbyte boundary Serial Communications Unit The Serial Control Unit (SCU) of the 80C186EB contains two independent channels Each channel is identical in operation except that only channel 0 is supported by the integrated interrupt controller (channel 1 has an external interrupt pin) Each channel has its own baud rate generator that is independent of the Timer Counter Unit and can be internally or externally clocked at up to one half the 80C186EB operating frequency Independent baud rate generators are provided for each of the serial channels For the asynchronous modes the generator supplies an 8x baud clock to both the receive and transmit register logic A 1x baud clock is provided in the synchronous mode Power Management Unit The 80C186EB Power Management Unit (PMU) is provided to control the power consumption of the device The PMU provides three power modes Active Idle and Powerdown Active Mode indicates that all units on the 80C186EB are functional and the device consumes maximum power (depending on the level of peripheral operation) Idle Mode freezes the clocks of the Execution and Bus units at a logic zero state (all peripherals continue to operate normally) The Powerdown mode freezes all internal clocks at a logic zero level and disables the crystal oscillator All internal registers hold their values provided VCC is maintained Current consumption is reduced to just transistor junction leakage Chip-Select Unit The 80C186EB Chip-Select Unit (CSU) integrates logic which provides up to ten programmable chipselects to access both memories and peripherals In addition each chip-select can be programmed to automatically insert additional clocks (wait-states) into the current bus cycle and automatically terminate a bus cycle independent of the condition of the READY input pin 80C187 Interface (80C186EB Only) The 80C186EB (PLCC package only) supports the direct connection of the 80C187 Numerics Coprocessor I O Port Unit The I O Port Unit (IPU) on the 80C186EB supports two 8-bit channels of input output or input output operation Port 1 is multiplexed with the chip select pins and is output only Most of Port 2 is multiplexed with the serial channel pins Port 2 pins are limited to either an output or input function depending on the operation of the serial pin it is multiplexed with ONCE Test Mode To facilitate testing and inspection of devices when fixed into a target system the 80C186EB has a test mode available which forces all output and input output pins to be placed in the high-impedance state ONCE stands for ``ON Circuit Emulation'' The ONCE mode is selected by forcing the A19 ONCE pin LOW (0) during a processor reset (this pin is weakly held to a HIGH (1) level) while RESIN is active Refresh Control Unit The Refresh Control Unit (RCU) automatically generates a periodic memory read bus cycle to keep dynamic or pseudo-static memory refreshed A 9-bit counter controls the number of clocks between refresh requests 7 7 80C186EB 80C188EB 80L186EB 80L188EB The Pin Type column contains two kinds of information The first symbol indicates whether a pin is power (P) ground (G) input only (I) output only (O) or input output (I O) Some pins have multiplexed functions (for example A19 S6) Additional symbols indicate additional characteristics for each pin Table 2 lists all the possible symbols for this column The Input Type column indicates the type of input (Asynchronous or Synchronous) Asynchronous pins require that setup and hold times be met only in order to guarantee recognition at a particular clock edge Synchronous pins require that setup and hold times be met to guarantee proper operation For example missing the setup or hold time for the SRDY pin (a synchronous input) will result in a system failure or lockup Input pins may also be edge- or level-sensitive The possible characteristics for input pins are S(E) S(L) A(E) and A(L) The Output States column indicates the output state as a function of the device operating mode Output states are dependent upon the current activity of the processor There are four operational states that are different from regular operation bus hold reset Idle Mode and Powerdown Mode Appropriate characteristics for these states are also indicated in this column with the legend for all possible characteristics in Table 2 The Pin Description column contains a text description of each pin As an example consider AD15 0 I O signifies the pins are bidirectional S(L) signifies that the input function is synchronous and level-sensitive H(Z) signifies that as outputs the pins are high-impedance upon acknowledgement of bus hold R(Z) signifies that the pins float during reset P(X) signifies that the pins retain their states during Powerdown Mode PACKAGE INFORMATION This section describes the pins pinouts and thermal characteristics for the 80C186EB in the Plastic Leaded Chip Carrier (PLCC) package Shrink Quad Flat Pack (SQFP) and Quad Flat Pack (QFP) package For complete package specifications and information see the Intel Packaging Outlines and Dimensions Guide (Order Number 231369) Prefix Identification With the extended temperature range operational characteristics are guaranteed over the temperature range corresponding to b 40 C to a 85 C ambient Package types are identified by a two-letter prefix to the part number The prefixes are listed in Table 1 Table 1 Prefix Identification Prefix Note TN TS SB N S 1 1 1 Package Type PLCC Temperature Type Extended QFP (EIAJ) Extended SQFP PLCC Extended Commercial Commercial QFP (EIAJ) Commercial NOTE 1 The 5V 25 MHz and 3V 16 MHz versions are only available in commercial temperature range corresponding to 0 C to a 70 C ambient Pin Descriptions Each pin or logical set of pins is described in Table 3 There are three columns for each entry in the Pin Description Table The Pin Name column contains a mnemonic that describes the pin function Negation of the signal name (for example RESIN) denotes a signal that is active low 8 8 80C186EB 80C188EB 80L186EB 80L188EB Table 2 Pin Description Nomenclature Symbol P G I O IO S(E) S(L) A(E) A(L) H(1) H(0) H(Z) H(Q) H(X) R(WH) R(1) R(0) R(Z) R(Q) R(X) I(1) I(0) I(Z) I(Q) I(X) P(1) P(0) P(Z) P(Q) P(X) Description Power Pin (Apply a VCC Voltage) Ground (Connect to VSS) Input Only Pin Output Only Pin Input Output Pin Synchronous Edge Sensitive Synchronous Level Sensitive Asynchronous Edge Sensitive Asynchronous Level Sensitive Output Driven to VCC during Bus Hold Output Driven to VSS during Bus Hold Output Floats during Bus Hold Output Remains Active during Bus Hold Output Retains Current State during Bus Hold Output Weakly Held at VCC during Reset Output Driven to VCC during Reset Output Driven to VSS during Reset Output Floats during Reset Output Remains Active during Reset Output Retains Current State during Reset Output Driven to VCC during Idle Mode Output Driven to VSS during Idle Mode Output Floats during Idle Mode Output Remains Active during Idle Mode Output Retains Current State during Idle Mode Output Driven to VCC during Powerdown Mode Output Driven to VSS during Powerdown Mode Output Floats during Powerdown Mode Output Remains Active during Powerdown Mode Output Retains Current State during Powerdown Mode 9 9 80C186EB 80C188EB 80L186EB 80L188EB Table 3 Pin Descriptions Pin Name VCC VSS CLKIN Pin Type P G I A(E) Input Type Output States Description POWER connections consist of four pins which must be shorted externally to a VCC board plane GROUND connections consist of six pins which must be shorted externally to a VSS board plane CLocK INput is an input for an external clock An external oscillator operating at two times the required processor operating frequency can be connected to CLKIN For crystal operation CLKIN (along with OSCOUT) are the crystal connections to an internal Pierce oscillator H(Q) R(Q) P(Q) OSCillator OUTput is only used when using a crystal to generate the external clock OSCOUT (along with CLKIN) are the crystal connections to an internal Pierce oscillator This pin is not to be used as 2X clock output for non-crystal applications (i e this pin is N C for non-crystal applications) OSCOUT does not float in ONCE mode CLocK OUTput provides a timing reference for inputs and outputs of the processor and is one-half the input clock (CLKIN) frequency CLKOUT has a 50% duty cycle and transistions every falling edge of CLKIN RESet IN causes the processor to immediately terminate any bus cycle in progress and assume an initialized state All pins will be driven to a known state and RESOUT will also be driven active The rising edge (low-to-high) transition synchronizes CLKOUT with CLKIN before the processor begins fetching opcodes at memory location 0FFFF0H H(0) R(1) P(0) A(L) H(WH) R(Z) P(1) RESet OUTput that indicates the processor is currently in the reset state RESOUT will remain active as long as RESIN remains active Power-Down TiMeR pin (normally connected to an external capacitor) that determines the amount of time the processor waits after an exit from power down before resuming normal operation The duration of time required will depend on the startup characteristics of the crystal oscillator Non-Maskable Interrupt input causes a TYPE-2 interrupt to be serviced by the CPU NMI is latched internally TEST is used during the execution of the WAIT instruction to suspend CPU operation until the pin is sampled active (LOW) TEST is alternately known as BUSY when interfacing with an 80C187 numerics coprocessor (80C186EB only) H(Z) R(Z) P(X) These pins provide a multiplexed Address and Data bus During the address phase of the bus cycle address bits 0 through 15 (0 through 7 on the 80C188EB) are presented on the bus and can be latched using ALE 8- or 16-bit data information is transferred during the data phase of the bus cycle OSCOUT O CLKOUT O H(Q) R(Q) P(Q) A(L) RESIN I RESOUT O PDTMR IO NMI TEST BUSY (TEST) I I A(E) A(E) AD15 0 (AD7 0) IO S(L) NOTE Pin names in parentheses apply to the 80C188EB 80L188EB 10 10 80C186EB 80C188EB 80L186EB 80L188EB Table 3 Pin Descriptions (Continued) Pin Name A18 16 A19 ONCE (A15 A8) (A18 16) (A19 ONCE) Pin Type IO Input Type A(L) Output States H(Z) R(WH) P(X) Description These pins provide multiplexed Address during the address phase of the bus cycle Address bits 16 through 19 are presented on these pins and can be latched using ALE These pins are driven to a logic 0 during the data phase of the bus cycle On the 80C188EB A15 - A8 provide valid address information for the entire bus cycle During a processor reset (RESIN active) A19 ONCE is used to enable ONCE mode A18 16 must not be driven low during reset or improper operation may result Bus cycle Status are encoded on these pins to provide bus transaction information S2 0 are encoded as follows S2 0 0 0 0 1 1 1 1 ALE O H(0) R(0) P(0) H(Z) R(Z) P(X) S1 0 0 1 1 0 0 1 1 S0 0 1 0 1 0 1 0 1 Bus Cycle Initiated Interrupt Acknowledge Read I O Write I O Processor HALT Queue Instruction Fetch Read Memory Write Memory Passive (no bus activity) S2 0 O H(Z) R(Z) P(1) Address Latch Enable output is used to strobe address information into a transparent type latch during the address phase of the bus cycle Byte High Enable output to indicate that the bus cycle in progress is transferring data over the upper half of the data bus BHE and A0 have the following logical encoding A0 0 0 1 1 BHE 0 1 0 1 Encoding (for the 80C186EB 80L186EB only) Word Transfer Even Byte Transfer Odd Byte Transfer Refresh Operation BHE (RFSH) O On the 80C188EB 80L188EB RFSH is asserted low to indicate a refresh bus cycle RD O H(Z) R(Z) P(1) H(Z) R(Z) P(1) A(L) S(L) H(Z) R(Z) P(1) ReaD output signals that the accessed memory or I O device must drive data information onto the data bus WRite output signals that data available on the data bus are to be written into the accessed memory or I O device READY input to signal the completion of a bus cycle READY must be active to terminate any bus cycle unless it is ignored by correctly programming the Chip-Select Unit Data ENable output to control the enable of bi-directional transceivers in a buffered system DEN is active only when data is to be transferred on the bus WR O READY I DEN O NOTE Pin names in parentheses apply to the 80C188EB 80L188EB 11 11 80C186EB 80C188EB 80L186EB 80L188EB Table 3 Pin Descriptions (Continued) Pin Name DT R Pin Type O Input Type Output States H(Z) R(Z) P(X) H(Z) R(WH) P(1) Description Data Transmit Receive output controls the direction of a bi-directional buffer in a buffered system DT R is only available for the PLCC package LOCK output indicates that the bus cycle in progress is not to be interrupted The processor will not service other bus requests (such as HOLD) while LOCK is active This pin is configured as a weakly held high input while RESIN is active and must not be driven low HOLD request input to signal that an external bus master wishes to gain control of the local bus The processor will relinquish control of the local bus between instruction boundaries not conditioned by a LOCK prefix H(1) R(0) P(0) HoLD Acknowledge output to indicate that the processor has relinquished control of the local bus When HLDA is asserted the processor will (or has) floated its data bus and control signals allowing another bus master to drive the signals directly Numerics Coprocessor Select output is generated when accessing a numerics coprocessor NCS is not provided on the QFP or SQFP packages This signal does not exist on the 80C188EB 80L188EB ERROR input that indicates the last numerics coprocessor operation resulted in an exception condition An interrupt TYPE 16 is generated if ERROR is sampled active at the beginning of a numerics operation ERROR is not provided on the QFP or SQFP packages This signal does not exist on the 80C188EB 80L188EB CoProcessor REQuest signals that a data transfer between an External Numerics Coprocessor and Memory is pending PEREQ is not provided on the QFP or SQFP packages This signal does not exist on the 80C188EB 80L188EB H(1) R(1) P(1) Upper Chip Select will go active whenever the address of a memory or I O bus cycle is within the address limitations programmed by the user After reset UCS is configured to be active for memory accesses between 0FFC00H and 0FFFFFH Lower Chip Select will go active whenever the address of a memory bus cycle is within the address limitations programmed by the user LCS is inactive after a reset These pins provide a multiplexed function If enabled each pin can provide a Generic Chip Select output which will go active whenever the address of a memory or I O bus cycle is within the address limitations programmed by the user When not programmed as a Chip-Select each pin may be used as a general purpose output Port As an output port pin the value of the pin can be read internally LOCK O HOLD I A(L) HLDA O NCS (N C ) O H(1) R(1) P(1) A(L) ERROR (N C ) I PEREQ (N C ) I A(L) UCS O LCS O H(1) R(1) P(1) H(X) H(1) R(1) P(X) P(1) P1 0 P1 1 P1 2 P1 3 P1 4 P1 5 P1 6 P1 7 GCS0 GCS1 GCS2 GCS3 GCS4 GCS5 GCS6 GCS7 O NOTE Pin names in parentheses apply to the 80C188EB 80L188EB 12 12 80C186EB 80C188EB 80L186EB 80L188EB Table 3 Pin Descriptions (Continued) Pin Name T0OUT T1OUT T0IN T1IN INT0 INT1 INT4 Pin Type O Input Type Output States H(Q) R(1) P(Q) A(L) A(E) A(E L) Description Timer OUTput pins can be programmed to provide a single clock or continuous waveform generation depending on the timer mode selected Timer INput is used either as clock or control signals depending on the timer mode selected Maskable INTerrupt input will cause a vector to a specific Type interrupt routine To allow interrupt expansion INT0 and or INT1 can be used with INTA0 and INTA1 to interface with an external slave controller H(1) R(Z) P(1) These pins provide a multiplexed function As inputs they provide a maskable INTerrupt that will cause the CPU to vector to a specific Type interrupt routine As outputs each is programmatically controlled to provide an INTERRUPT ACKNOWLEDGE handshake signal to allow interrupt expansion BI-DIRECTIONAL open-drain Port pins I I INT2 INTA0 INT3 INTA1 IO A(E L) P2 7 P2 6 CTSO P2 4 CTS1 IO A(L) H(X) R(Z) P(X) I A(L) Clear-To-Send input is used to prevent the transmission of serial data on their respective TXD signal pin CTS1 is multiplexed with an input only port function H(X) H(Q) R(1) P(X) P(Q) Transmit Data output provides serial data information TXD1 is multiplexed with an output only Port function During synchronous serial communications TXD will function as a clock output Receive Data input accepts serial data information RXD1 is multiplexed with an input only Port function During synchronous serial communications RXD is bi-directional and will become an output for transmission or data (TXD becomes the clock) Baud CLocK input can be used as an alternate clock source for each of the integrated serial channels BCLKx is multiplexed with an input only Port function and cannot exceed a clock rate greater than one-half the operating frequency of the processor H(X) H(Q) R(0) P(X) P(X) Serial INTerrupt output will go active to indicate serial channel 1 requires service SINT1 is multiplexed with an output only Port function TXD0 P2 1 TXD1 O RXD0 P2 0 RXD1 IO A(L) R(Z) H(Q) P(X) P2 5 BCLK0 P2 2 BCLK1 I A(L) A(E) P2 3 SINT1 O NOTE Pin names in parentheses apply to the 80C188EB 80L188EB 13 13 80C186EB 80C188EB 80L186EB 80L188EB Tables 6 and 7 list the 80C186EB 80C188EB pin names with package location for the 80-pin Quad Flat Pack (QFP) component Figure 6 depicts the complete 80C186EB 80C188EB (QFP package) as viewed from the top side of the component (i e contacts facing down) Tables 8 and 9 list the 80186EB 80188EB pin names with package location for the 80-pin Shrink Quad Flat Pack (SQFP) component Figure 7 depicts the complete 80C186EB 80C188EB (SQFP package) as viewed from the top side of the component (i e contacts facing down) 80C186EB PINOUT Tables 4 and 5 list the 80C186EB 80C188EB pin names with package location for the 84-pin Plastic Leaded Chip Carrier (PLCC) component Figure 5 depicts the complete 80C186EB 80C188EB pinout (PLCC package) as viewed from the top side of the component (i e contacts facing down) Table 4 PLCC Pin Names with Package Location Address Data Bus Name AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 (A8) AD9 (A9) AD10 (A10) AD11 (A11) AD12 (A12) AD13 (A13) AD14 (A14) AD15 (A15) A16 A17 A18 A19 ONCE Location 61 66 68 70 72 74 76 78 62 67 69 71 73 75 77 79 80 81 82 83 Bus Control Name ALE BHE (RFSH) S0 S1 S2 RD WR READY DEN DT R LOCK HOLD HLDA Power Name VSS VCC Location 2 22 43 63 65 84 1 23 42 64 Location 6 7 10 9 8 4 5 18 11 16 15 13 12 Processor Control Name RESIN RESOUT CLKIN OSCOUT CLKOUT TEST BUSY NCS (N C ) PEREQ (N C ) ERROR (N C ) PDTMR NMI INT0 INT1 INT2 INTA0 INT3 INTA1 INT4 Location 37 38 41 40 44 14 60 39 3 36 17 31 32 33 34 35 Name UCS LCS P1 0 P1 1 P1 2 P1 3 P1 4 P1 5 P1 6 P1 7 IO Location 30 29 28 27 26 25 24 21 20 19 45 46 47 48 53 52 54 51 57 58 59 55 56 50 49 GCS0 GCS1 GCS2 GCS3 GCS4 GCS5 GCS6 GCS7 T0OUT T0IN T1OUT T1IN RXD0 TXD0 P2 5 BCLK0 CTS0 P2 0 P2 1 P2 2 P2 3 P2 4 P2 6 P2 7 RXD1 TXD1 BCLK1 SINT1 CTS1 NOTE Pin names in parentheses apply to the 80C188EB 80L188EB 14 14 80C186EB 80C188EB 80L186EB 80L188EB Table 5 PLCC Package Locations with Pin Name Location 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 Name VCC VSS ERROR (N C ) RD WR ALE BHE (RFSH) S2 S1 S0 DEN HLDA HOLD TEST BUSY LOCK DT R NMI READY P1 7 GCS7 P1 6 GCS6 P1 5 GCS5 Location 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 Name VSS VCC P1 4 GCS4 P1 3 GCS3 P1 2 GCS2 P1 1 GCS1 P1 0 GCS0 LCS UCS INT0 INT1 INT2 INTA0 INT3 INTA1 INT4 PDTMR RESIN RESOUT PEREQ (N C ) OSCOUT CLKIN VCC Location 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 Name VSS CLKOUT T0OUT T0IN T1OUT T1IN P2 7 P2 6 CTS0 TXD0 RXD0 P2 5 BCLK0 P2 3 SINT1 P2 4 CTS1 P2 0 RXD1 P2 1 TXD1 P2 2 BCLK1 NCS (N C ) AD0 AD8 (A8) VSS Location 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 Name VCC VSS AD1 AD9 (A9) AD2 AD10 (A10) AD3 AD11 (A11) AD4 AD12 (A12) AD5 AD13 (A13) AD6 AD14 (A14) AD7 AD15 (A15) A16 A17 A18 A19 ONCE VSS NOTE Pin names in parentheses apply to the 80C188EB 80L188EB 15 15 80C186EB 80C188EB 80L186EB 80L188EB 272433 - 5 NOTE This is the FPO number location (indicated by X's) Pin names in parentheses apply to the 80C188EB 80L188EB Figure 4 84-Pin Plastic Leaded Chip Carrier Pinout Diagram 16 16 80C186EB 80C188EB 80L186EB 80L188EB Table 6 QFP Pin Name with Package Location Address Data Bus Name AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 (A8) AD9 (A9) AD10 (A10) AD11 (A11) AD12 (A12) AD13 (A13) AD14 (A14) AD15 (A15) A16 A17 A18 A19 ONCE Location 10 15 17 19 21 23 25 27 11 16 18 20 22 24 26 28 29 30 31 32 Bus Control Name ALE BHE (RFSH) S0 S1 S2 RD WR READY DEN LOCK HOLD HLDA Power Name VSS VCC Location 12 14 33 35 53 73 13 34 54 72 Location 38 39 42 41 40 36 37 49 43 47 45 44 Processor Control Name RESIN RESOUT CLKIN OSCOUT CLKOUT TEST PDTMR NMI INT0 INT1 INT2 INTA0 INT3 INTA1 INT4 Location 68 69 71 70 74 46 67 48 62 63 64 65 66 Name UCS LCS P1 0 GCS0 P1 1 GCS1 P1 2 GCS2 P1 3 GCS3 P1 4 GCS4 P1 5 GCS5 P1 6 GCS6 P1 7 GCS7 T0OUT T0IN T1OUT T1IN RXD0 TXD0 P2 5 BCLK0 CTS0 P2 0 RXD1 P2 1 TXD1 P2 2 BCLK1 P2 3 SINT1 P2 4 CTS1 P2 6 P2 7 NOTE Pin names in parentheses apply to the 80C188EB 80L188EB IO Location 61 60 59 58 57 56 55 52 51 50 75 76 77 78 3 2 4 1 7 8 9 5 6 80 79 17 17 80C186EB 80C188EB 80L186EB 80L188EB Table 7 QFP Package Location with Pin Names Location 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Name CTS0 TXD0 RXD0 P2 5 BCLK0 P2 3 SINT1 P2 4 CTS1 P2 0 RXD1 P2 1 TXD1 P2 2 BCLK1 AD0 AD8 (A8) VSS VCC VSS AD1 AD9 (A9) AD2 AD10 (A10) AD3 AD11 (A11) Location 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Name AD4 AD12 (A12) AD5 AD13 (A13) AD6 AD14 (A14) AD7 AD15 (A15) A16 A17 A18 A19 ONCE VSS VCC VSS RD WR ALE BHE (RFSH) S2 Location 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 Name S1 S0 DEN HLDA HOLD TEST LOCK NMI READY P1 7 GCS7 P1 6 GCS6 P1 5 GCS5 VSS VCC P1 4 GCS4 P1 3 GCS3 P1 2 GCS2 P1 1 GCS1 P1 0 GCS0 LCS Location 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 Name UCS INT0 INT1 INT2 INTA0 INT3 INTA1 INT4 PDTMR RESIN RESOUT OSCOUT CLKIN VCC VSS CLKOUT T0OUT T0IN T1OUT T1IN P2 7 P2 6 NOTE Pin names in parentheses apply to the 80C188EB 80L188EB 18 18 80C186EB 80C188EB 80L186EB 80L188EB 272433 - 6 NOTE This is the FPO number location (indicated by X's) Pin names in parentheses apply to the 80C188EB 80L188EB Figure 5 Quad Flat Pack Pinout Diagram 19 19 80C186EB 80C188EB 80L186EB 80L188EB Table 8 SQFP Pin Functions with Location AD Bus AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 (A8) AD9 (A9) AD10 (A10) AD11 (A11) AD12 (A12) AD13 (A13) AD14 (A14) AD15 (A15) A16 A17 A18 A19 ONCE 47 52 54 56 58 60 62 64 48 53 55 57 59 61 63 65 66 67 68 69 Bus Control ALE BHE (RFSH ) S0 S1 S2 RD WR READY DEN LOCK HOLD HLDA 75 76 79 78 77 73 74 6 80 4 2 1 Processor Control RESIN RESOUT CLKIN OSCOUT CLKOUT TEST BUSY NMI INT0 INT1 INT2 INTA0 INT3 INTA1 INT4 PDTMR 25 26 28 27 31 3 5 19 20 21 22 23 24 UCS LCS P1 0 P1 1 P1 2 P1 3 P1 4 P1 5 P1 6 P1 7 P2 0 P2 1 P2 2 P2 3 P2 4 P2 5 P2 6 P2 7 GCS0 GCS1 GCS2 GCS3 GCS4 GCS5 GCS6 GCS7 RXD1 TXD1 BCLK1 SINT1 CTS1 BCLK0 IO 18 17 16 15 14 13 12 9 8 7 44 45 46 42 43 41 37 36 38 39 40 33 35 32 34 Power and Ground VCC VCC VCC VCC VSS VSS VSS VSS VSS VSS 11 29 50 71 10 30 49 51 70 72 CTS0 TXD0 RXD0 T0IN T1IN T0OUT T1OUT Table 9 SQFP Pin Locations with Pin Names 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 HLDA HOLD TEST LOCK NMI READY P1 7 GCS7 P1 6 GCS6 P1 5 GCS5 VSS VCC P1 4 GCS4 P1 3 GCS3 P1 2 GCS2 P1 1 GCS1 P1 0 GCS0 LCS UCS INT0 INT1 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 INT1 INTA0 INT3 INTA1 INT4 PDTMR RESIN RESOUT OSCOUT CLKIN VCC VSS CLKOUT T0OUT T0IN T1OUT T1IN P2 7 P2 6 CTS0 TXD0 RXD0 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 P2 5 BCLK0 P2 3 SINT1 P2 4 CTS1 P2 0 RXD1 P2 1 TXD1 P2 2 BCLK1 AD0 AD8 (A8) VSS VCC VSS AD1 AD9 (A9) AD2 AD10 (A10) AD3 AD11 (A11) AD4 AD12 (A12) AD5 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 AD13 (A13) AD6 AD14 (A14) AD7 AD15 (A15) A16 A17 A18 A19 ONCE VSS VCC VSS RD WR ALE BHE (RFSH ) S2 S1 S0 DEN NOTE Pin names in parentheses apply to the 80C188EB 80L188EB 20 20 80C186EB 80C188EB 80L186EB 80L188EB 272433 - 7 NOTE XXXXXXXXC indicates Intel FPO number Pin names in parentheses apply to the 80C188EB 80L188EB Figure 6 SQFP Package 21 21 80C186EB 80C188EB 80L186EB 80L188EB TA (the ambient temperature) can be calculated from iCA (thermal resistance from the case to ambient) with the following equation TA e TC b P iCA PACKAGE THERMAL SPECIFICATIONS The 80C186EB 80L186EB is specified for operation when TC (the case temperature) is within the range of b 40 C to a 100 C (PLCC package) or b 40 C to a 114 C (QFP package) TC may be measured in any environment to determine whether the processor is within the specified operating range The case temperature must be measured at the center of the top surface Typical values for iCA at various airflows are given in Table 10 P (the maximum power consumption specified in watts) is calculated by using the maximum ICC as tabulated in the DC specifications and VCC of 5 5V Table 10 Thermal Resistance (iCA) at Various Airflows (in C Watt) Airflow Linear ft min (m sec) 0 200 400 600 800 1000 (0) (1 01) (2 03) (3 04) (4 06) (5 07) iCA (PLCC) iCA (QFP) iCA (SQFP) 30 58 70 24 47 TBD 21 43 TBD 19 40 TBD 17 38 TBD 16 5 36 TBD 22 22 80C186EB 80C188EB 80L186EB 80L188EB ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings Storage Temperature Case Temp under Bias Supply Voltage with Respect to VSS Voltage on other Pins with Respect to VSS b 65 C to a 150 C b 65 C to a 120 C b 0 5V to a 6 5V b 0 5V to VCC a 0 5V NOTICE This data sheet contains preliminary information on new products in production It is valid for the devices indicated in the revision history The specifications are subject to change without notice WARNING Stressing the device beyond the ``Absolute Maximum Ratings'' may cause permanent damage These are stress ratings only Operation beyond the ``Operating Conditions'' is not recommended and extended exposure beyond the ``Operating Conditions'' may affect device reliability Recommended Connections Power and ground connections must be made to multiple VCC and VSS pins Every 80C186EB-based circuit board should include separate power (VCC) and ground (VSS) planes Every VCC pin must be connected to the power plane and every VSS pin must be connected to the ground plane Pins identified as ``NC'' must not be connected in the system Liberal decoupling capacitance should be placed near the processor The processor can cause transient power surges when its output buffers transition particularly when connected to large capacitive loads Low inductance capacitors and interconnects are recommended for best high frequency electrical performance Inductance is reduced by placing the decoupling capacitors as close as possible to the processor VCC and VSS package pins Always connect any unused input to an appropriate signal level In particular unused interrupt inputs (INT0 4) should be connected to VCC through a pullup resistor (in the range of 50 KX) Leave any unused output pin or any NC pin unconnected 23 23 80C186EB 80C188EB 80L186EB 80L188EB DC SPECIFICATIONS (80C186EB 80C188EB) Symbol VCC VIL VIH VOL VOH VHYR ILI1 Parameter Supply Voltage Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Input Hysterisis on RESIN Input Leakage Current for Pins AD15 0 (AD7 0) READY HOLD RESIN CLKIN TEST NMI INT4 0 T0IN T1IN RXD0 BCLK0 CTS0 RXD1 BCLK1 CTS1 P2 6 P2 7 Input Leakage Current for Pins ERROR PEREQ Input Leakage Current for Pins A19 ONCE A18 16 LOCK Output Leakage Current Supply Current Cold (RESET) 80C186EB25 80C186EB20 80C186EB13 IID Supply Current Idle 80C186EB25 80C186EB20 80C186EB13 IPD Supply Current Powerdown 80C186EB25 80C186EB20 80C186EB13 CIN COUT Input Pin Capacitance Output Pin Capacitance 0 0 g0 275 Min 45 b0 5 Max 55 0 3 VCC VCC a 0 5 0 45 Units V V V V V V Notes 0 7 VCC VCC b 0 5 0 50 IOL e 3 mA (Min) IOH e b 2 mA (MIn) 0V s VIN s VCC g15 mA ILI2 ILI3 ILO ICC g7 mA mA mA 0V s VIN k VCC VIN e 0 7 VCC (Note 1) 0 45 s VOUT s VCC (Note 2) (Notes 3 7) (Note 3) (Note 3) (Notes 4 7) (Note 4) (Note 4) (Notes 5 7) (Note 5) (Note 5) TF e 1 MHz TF e 1 MHz (Note 6) b 0 275 b5 0 g15 115 108 73 91 76 48 100 100 100 15 15 mA mA mA mA mA mA mA mA mA pF pF NOTES 1 These pins have an internal pull-up device that is active while RESIN is low and ONCE Mode is not active Sourcing more current than specified (on any of these pins) may invoke a factory test mode 2 Tested by outputs being floated by invoking ONCE Mode or by asserting HOLD 3 Measured with the device in RESET and at worst case frequency VCC and temperature with ALL outputs loaded as specified in AC Test Conditions and all floating outputs driven to VCC or GND 4 Measured with the device in HALT (IDLE Mode active) and at worst case frequency VCC and temperature with ALL outputs loaded as specified in AC Test Conditions and all floating outputs driven to VCC or GND 5 Measured with the device in HALT (Powerdown Mode active) and at worst case frequency VCC and temperature with ALL outputs loaded as specified in AC Test Conditions and all floating outputs driven to VCC or GND 6 Output Capacitance is the capacitive load of a floating output pin 7 Operating temperature for 25 MHz is 0 C to 70 C VCC e 5 0 g10% 24 24 80C186EB 80C188EB 80L186EB 80L188EB DC SPECIFICATIONS (80L186EB16) Symbol VCC VIL VIH VOL VOH VHYR ILI1 Parameter Supply Voltage Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Input Hysterisis on RESIN Input Leakage Current for pins AD15 0 (AD7 0) READY HOLD RESIN CLKIN TEST NMI INT4 0 T0IN T1IN RXD0 BCLK0 CTS0 RXD1 BCLK1 CTS1 SINT1 P2 6 P2 7 Input Leakage Current for Pins A19 ONCE A18 16 LOCK Output Leakage Current Supply Current (RESET 3 3V) 80L186EB16 Supply Current Idle (3 3V) 80L186EB16 Supply Current Powerdown (3 3V) 80L186EB16 Input Pin Capacitance Output Pin Capacitance (operating temperature 0 C to 70 C) Min 30 b0 5 Max 55 0 3 VCC VCC a 0 5 0 45 Units V V V V V V Notes 0 7 VCC VCC b 0 5 0 50 IOL e 1 6 mA (Min) (Note 1) IOH e b 1 mA (Min) (Note 1) 0V s VIN s VCC g15 mA ILI2 ILO ICC3 IID3 IPD3 CIN COUT b 0 275 b2 mA mA mA mA mA pF pF VIN e 0 7 VCC (Note 2) 0 45 s VOUT s VCC (Note 3) (Note 4) (Note 5) (Note 6) TF e 1 MHz TF e 1 MHz (Note 7) g15 54 38 40 0 0 15 15 NOTES 1 IOL and IOH measured at VCC e 3 0V 2 These pins have an internal pull-up device that is active while RESIN is low and ONCE Mode is not active Sourcing more current than specified (on any of these pins) may invoke a factory test mode 3 Tested by outputs being floated by invoking ONCE Mode or by asserting HOLD 4 Measured with the device in RESET and at worst case frequency VCC and temperature with ALL outputs loaded as specified in AC Test Conditions and all floating outputs driven to VCC or GND 5 Measured with the device in HALT (IDLE Mode active) and at worst case frequency VCC and temperature with ALL outputs loaded as specified in AC Test Conditions and all floating outputs driven to VCC or GND 6 Measured with the device in HALT (Powerdown Mode active) and at worst case frequency VCC and temperature with ALL outputs loaded as specified in AC Test Conditions and all floating outputs driven to VCC or GND 7 Output Capacitance is the capacitive load of a floating output pin 25 25 80C186EB 80C188EB 80L186EB 80L188EB DC SPECIFICATIONS (80L186EB13 80L188EB13 80L186EB8 80L188EB8) Symbol VCC VIL VIH VOL VOH VHYR ILI1 Parameter Supply Voltage Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Input Hysterisis on RESIN Input Leakage Current for pins AD15 0 (AD7 0) READY HOLD RESIN CLKIN TEST NMI INT4 0 T0IN T1IN RXD0 BCLK0 CTS0 RXD1 BCLK1 CTS1 SINT1 P2 6 P2 7 Input Leakage Current for Pins A19 ONCE A18 16 LOCK Output Leakage Current Supply Current (RESET 5 5V) 80L186EB13 80L186EB8 Supply Current (RESET 2 7V) 80L186EB13 80L186EB8 Supply Current Idle (5 5V) 80L186EB13 80L186EB8 Supply Current Idle (2 7V) 80L186EB13 80L186EB8 Supply Current Powerdown (5 5V) 80L186EB13 80L186EB8 Supply Current Powerdown (2 7V) 80L186EB13 80L186EB8 Input Pin Capacitance Output Pin Capacitance 0 0 b 0 275 Min 27 b0 5 Max 55 0 3 VCC VCC a 0 5 0 45 Units V V V V V V Notes 0 7 VCC VCC b 0 5 0 50 IOL e 1 6 mA (Min) (Note 1) IOH e b 1 mA (Min) (Note 1) 0V s VIN s VCC g15 mA ILI2 ILO ICC5 b2 mA mA mA mA mA mA mA mA mA mA mA mA mA mA pF pF VIN e 0 7 VCC (Note 2) 0 45 s VOUT s VCC (Note 3) (Note 4) (Note 4) (Note 4) (Note 4) (Note 5) (Note 5) (Note 5) (Note 5) (Note 6) (Note 6) (Note 6) (Note 6) TF e 1 MHz TF e 1 MHz (Note 7) g15 73 45 36 22 48 31 24 15 100 100 30 30 15 15 ICC3 IID5 IID3 IPD5 IPD3 CIN COUT NOTES 1 IOL and IOH measured at VCC e 2 7V 2 These pins have an internal pull-up device that is active while RESIN is low and ONCE Mode is not active Sourcing more current than specified (on any of these pins) may invoke a factory test mode 3 Tested by outputs being floated by invoking ONCE Mode or by asserting HOLD 4 Measured with the device in RESET and at worst case frequency VCC and temperature with ALL outputs loaded as specified in AC Test Conditions and all floating outputs driven to VCC or GND 5 Measured with the device in HALT (IDLE Mode active) and at worst case frequency VCC and temperature with ALL outputs loaded as specified in AC Test Conditions and all floating outputs driven to VCC or GND 6 Measured with the device in HALT (Powerdown Mode active) and at worst case frequency VCC and temperature with ALL outputs loaded as specified in AC Test Conditions and all floating outputs driven to VCC or GND 7 Output Capacitance is the capacitive load of a floating output pin 26 26 80C186EB 80C188EB 80L186EB 80L188EB ICC VERSUS FREQUENCY AND VOLTAGE The current (ICC) consumption of the processor is essentially composed of two components IPD and ICCS IPD is the quiescent current that represents internal device leakage and is measured with all inputs or floating outputs at GND or VCC (no clock applied to the device) IPD is equal to the Powerdown current and is typically less than 50 mA ICCS is the switching current used to charge and discharge parasitic device capacitance when changing logic levels Since ICCS is typically much greater than IPD IPD can often be ignored when calculating ICC ICCS is related to the voltage and frequency at which the device is operating It is given by the formula Power e V c I e V2 c CDEV c f I e ICC e ICCS e V c CDEV c f PDTMR PIN DELAY CALCULATION The PDTMR pin provides a delay between the assertion of NMI and the enabling of the internal clocks when exiting Powerdown A delay is required only when using the on-chip oscillator to allow the crystal or resonator circuit time to stabilize NOTE The PDTMR pin function does not apply when RESIN is asserted (i e a device reset during Powerdown is similar to a cold reset and RESIN must remain active until after the oscillator has stabilized) To calculate the value of capacitor required to provide a desired delay use the equation 440 c t e CPD (5V 25 C) Where t e desired delay in seconds CPD e capacitive load on PDTMR in microfarads EXAMPLE To get a delay of 300 ms a capacitor value of CPD e 440 c (300 c 10b6) e 0 132 mF is required Round up to standard (available) capacitive values NOTE The above equation applies to delay times greater than 10 ms and will compute the TYPICAL capacitance needed to achieve the desired delay A delay variance of a 50% or b 25% can occur due to temperature voltage and device process extremes In general higher VCC and or lower temperature will decrease delay time while lower VCC and or higher temperature will increase delay time Where V e Device operating voltage (VCC) CDEV e Device capacitance f e Device operating frequency ICCS e ICC e Device current Measuring CDEV on a device like the 80C186EB would be difficult Instead CDEV is calculated using the above formula by measuring ICC at a known VCC and frequency (see Table 11) Using this CDEV value ICC can be calculated at any voltage and frequency within the specified operating range EXAMPLE Calculate the typical ICC when operating at 10 MHz 4 8V ICC e ICCS e 4 8 c 0 583 c 10 28 mA Table 11 Device Capacitance (CDEV) Values Parameter CDEV (Device in Reset) CDEV (Device in Idle) Typ 0 583 0 408 Max 1 02 0 682 Units mA V MHz mA V MHz Notes 12 12 1 Max CDEV is calculated at b40 C all floating outputs driven to VCC or GND and all outputs loaded to 50 pF (including CLKOUT and OSCOUT) 2 Typical CDEV is calculated at 25 C with all outputs loaded to 50 pF except CLKOUT and OSCOUT which are not loaded 27 27 80C186EB 80C188EB 80L186EB 80L188EB AC SPECIFICATIONS AC Characteristics Symbol INPUT CLOCK TF TC TCH TCL TCR TCF TCD T TPH TPL TPR TPF TCHOV1 TCHOV2 TCLOV1 TCLOV2 TCHOF TCLOF CLKIN Frequency CLKIN Period CLKIN High Time CLKIN Low Time CLKIN Rise Time CLKIN Fall Time 0 20 8 8 1 1 50 % % % 7 7 MHz ns ns ns ns ns 1 1 12 12 13 13 80C186EB25 Parameter 25 MHz Min Max Units Notes OUTPUT CLOCK CLKIN to CLKOUT Delay CLKOUT Period CLKOUT High Time CLKOUT Low Time CLKOUT Rise Time CLKOUT Fall Time 0 (T 2) b 5 (T 2) b 5 1 1 16 2 TC (T 2) a 5 (T 2) a 5 6 6 ns ns ns ns ns ns 14 1 1 1 15 15 OUTPUT DELAYS ALE S2 0 DEN DT R BHE (RFSH) LOCK A19 16 GCS0 7 LCS UCS NCS RD WR BHE (RFSH) DEN LOCK RESOUT HLDA T0OUT T1OUT A19 16 RD WR GCS7 0 LCS UCS AD15 0 (AD7 0 A15 8) NCS INTA1 0 S2 0 RD WR BHE (RFSH) DT R LOCK S2 0 A19 16 DEN AD15 0 (AD7 0 A15 8) 3 3 3 3 0 0 17 20 17 20 20 20 ns ns ns ns ns ns 1467 1468 146 146 1 1 28 28 80C186EB 80C188EB 80L186EB 80L188EB AC SPECIFICATIONS AC Characteristics Symbol SYNCHRONOUS INPUTS TCHIS TCHIH TCLIS TCLIH TCLIS TCLIH TEST NMI INT4 0 BCLK1 0 T1 0IN READY CTS1 0 P2 6 P2 7 TEST NMI INT4 0 BCLK1 0 T1 0IN READY CTS1 0 AD15 0 (AD7 0) READY READY AD15 0 (AD7 0) HOLD PEREQ ERROR HOLD PEREQ ERROR 10 3 10 3 10 3 ns ns ns ns ns ns 19 19 1 10 1 10 19 19 80C186EB25 (Continued) Parameter 25 MHz Min Max Units Notes NOTES 1 See AC Timing Waveforms for waveforms and definition 2 Measure at VIH for high time VIL for low time 3 Only required to guarantee ICC Maximum limits are bounded by TC TCH and TCL 4 Specified for a 50 pF load see Figure 13 for capacitive derating information 5 Specified for a 50 pF load see Figure 14 for rise and fall times outside 50 pF 6 See Figure 14 for rise and fall times 7 TCHOV1 applies to BHE (RFSH) LOCK and A19 16 only after a HOLD release 8 TCHOV2 applies to RD and WR only after a HOLD release 9 Setup and Hold are required to guarantee recognition 10 Setup and Hold are required for proper operation 29 29 80C186EB 80C188EB 80L186EB 80L188EB AC SPECIFICATIONS AC Characteristics Symbol INPUT CLOCK TF TC TCH TCL TCR TCF TCD T TPH TPL TPR TPF TCHOV1 CLKIN Frequency CLKIN Period CLKIN High Time CLKIN Low Time CLKIN Rise Time CLKIN Fall Time 0 25 10 10 1 1 40 % % % 8 8 0 38 5 12 12 1 1 26 % % % 8 8 MHz ns ns ns ns ns 1 1 12 12 13 13 80C186EB20 80C186EB13 20 MHz Min Max Min 13 MHz Max Units Notes Parameter OUTPUT CLOCK CLKIN to CLKOUT Delay CLKOUT Period CLKOUT High Time CLKOUT Low Time CLKOUT Rise Time CLKOUT Fall Time 0 (T 2) b 5 (T 2) b 5 1 1 17 2 TC (T 2) a 5 (T 2) a 5 6 6 0 (T 2) b 5 (T 2) b 5 1 1 23 2 TC (T 2) a 5 (T 2) a 5 6 6 ns ns ns ns ns ns 14 1 1 1 15 15 OUTPUT DELAYS ALE S2 0 DEN DT R BHE (RFSH) LOCK A19 16 GCS0 7 LCS UCS NCS RD WR BHE (RFSH) DEN LOCK RESOUT HLDA T0OUT T1OUT A19 16 RD WR GCS7 0 LCS UCS AD15 0 (AD7 0 A15 8) NCS INTA1 0 S2 0 RD WR BHE (RFSH) DT R LOCK S2 0 A19 16 DEN AD15 0 (AD7 0 A15 8) 3 22 3 25 ns 1467 TCHOV2 TCLOV1 3 3 27 22 3 3 30 25 ns ns 1468 146 TCLOV2 3 27 3 30 ns 146 TCHOF TCLOF 0 0 25 25 0 0 25 25 ns ns 1 1 30 30 80C186EB 80C188EB 80L186EB 80L188EB AC SPECIFICATIONS AC Characteristics Symbol SYNCHRONOUS INPUTS TCHIS TCHIH TCLIS TCLIH TCLIS TCLIH TEST NMI INT4 0 BCLK1 0 T1 0IN READY CTS1 0 P2 6 P2 7 TEST NMI INT4 0 BCLK1 0 T1 0IN READY CTS1 0 AD15 0 (AD7 0) READY READY AD15 0 (AD7 0) HOLD PEREQ ERROR HOLD PEREQ ERROR 10 3 10 3 10 3 10 3 10 3 10 3 ns ns ns ns ns ns 19 19 1 10 1 10 19 19 80C186EB20 80C186EB13 (Continued) Parameter 20 MHz Min Max 13 MHz Min Max Units Notes NOTES 1 See AC Timing Waveforms for waveforms and definition 2 Measure at VIH for high time VIL for low time 3 Only required to guarantee ICC Maximum limits are bounded by TC TCH and TCL 4 Specified for a 50 pF load see Figure 13 for capacitive derating information 5 Specified for a 50 pF load see Figure 14 for rise and fall times outside 50 pF 6 See Figure 14 for rise and fall times 7 TCHOV1 applies to BHE (RFSH) LOCK and A19 16 only after a HOLD release 8 TCHOV2 applies to RD and WR only after a HOLD release 9 Setup and Hold are required to guarantee recognition 10 Setup and Hold are required for proper operation 31 31 80C186EB 80C188EB 80L186EB 80L188EB AC SPECIFICATIONS AC Characteristics Symbol INPUT CLOCK TF TC TCH TCL TCR TCF TCD T TPH TPL TPR TPF TCHOV1 TCHOV2 TCHOV3 TCHOV4 TCHOV5 TCLOV1 TCLOV2 TCHOF TCLOF TCLOV3 TCLOV5 CLKIN Frequency CLKIN Period CLKIN High Time CLKIN Low Time CLKIN Rise Time CLKIN Fall Time 0 31 25 13 13 1 1 32 % % % 8 8 MHz ns ns ns ns ns 1 1 12 12 13 13 80L186EB16 Parameter 16 MHz Min Max Units Notes OUTPUT CLOCK CLKIN to CLKOUT Delay CLKOUT Period CLKOUT High Time CLKOUT Low Time CLKOUT Rise Time CLKOUT Fall Time 0 (T 2) b 5 (T 2) b 5 1 1 30 2 TC (T 2) a 5 (T 2) a 5 9 9 ns ns ns ns ns ns 14 1 1 1 15 15 OUTPUT DELAYS DT R LOCK A19 16 RFSH GCS0 7 LCS UCS NCS RD WR BHE DEN ALE S2 0 LOCK RESOUT HLDA T0OUT T1OUT A19 16 RD WR GCS7 0 LCS UCS NCS INTA1 0 AD15 0 (AD7 0 A15 8) RD WR BHE (RFSH) DT R LOCK S2 0 A19 16 DEN AD15 0 (AD7 0 A15 8) BHE DEN S2 0 3 3 3 3 3 3 3 0 0 3 3 22 27 25 30 33 22 27 25 25 25 33 ns ns ns ns ns ns ns ns ns ns ns 1467 1468 14 14 14 146 146 1 1 146 146 32 32 80C186EB 80C188EB 80L186EB 80L188EB AC SPECIFICATIONS AC Characteristics Symbol SYNCHRONOUS INPUTS TCHIS TCHIH TCLIS TCLIH TCLIS TCLIH TEST NMI INT4 0 BCLK1 0 T1 0IN READY CTS1 0 P2 6 P2 7 TEST NMI INT4 0 T1 0IN BCLK1 0 READY CTS1 0 AD15 0 (AD7 0) READY READY AD15 0 (AD7 0) HOLD HOLD 15 3 15 3 15 3 ns ns ns ns ns ns 19 19 1 10 1 10 19 19 80L186EB16 (Continued) Parameter 16 MHz Min Max Units Notes NOTES 1 See AC Timing Waveforms for waveforms and definition 2 Measure at VIH for high time VIL for low time 3 Only required to guarantee ICC Maximum limits are bounded by TC TCH and TCL 4 Specified for a 50 pF load see Figure 13 for capacitive derating information 5 Specified for a 50 pF load see Figure 14 for rise and fall times outside 50 pF 6 See Figure 14 for rise and fall times 7 TCHOV1 applies to BHE (RFSH) LOCK and A19 16 only after a HOLD release 8 TCHOV2 applies to RD and WR only after a HOLD release 9 Setup and Hold are required to guarantee recognition 10 Setup and Hold are required for proper operation 33 33 80C186EB 80C188EB 80L186EB 80L188EB AC SPECIFICATIONS AC Characteristics Symbol INPUT CLOCK Tr TC TCH TCL TCR TCF TCD T TPH TPL TPR TPF TCHOV1 CLKIN Frequency CLKIN Period CLKIN High Time CLKIN Low Time CLKIN Rise Time CLKIN Fall Time CLKIN to CLKOUT Delay CLKOUT Period CLKOUT High Time CLKOUT Low Time CLKOUT Rise Time CLKOUT Fall Time ALE S2-0 DEN DT R BHE (RFSH) LOCK A19 16 GCS0 7 LCS UCS NCS RD WR BHE (RFSH) DEN LOCK RESOUT HLDA T0OUT T1OUT A19 16 S2 0 RD WR GCS7 0 LCS UCS NCS INTA1 0 AD15 0 (AD7 0 A15 8) RD WR BHE (RFSH) DT R LOCK S2 0 A19 16 DEN AD15 0 (AD7 0 A15 8) 0 38 5 15 15 1 1 0 (T 2) b 5 (T 2) b 5 1 1 3 26 % % % 8 8 10 2 TC (T 2) a 5 (T 2) a 5 10 10 25 0 62 5 15 15 1 1 0 (T 2) b 5 (T 2) b 5 1 1 3 16 % % % 8 8 50 2 TC (T 2) a 5 (T 2) a 5 15 15 30 MHz ns ns ns ns ns ns ns ns ns ns ns ns 1 1 12 12 13 13 14 1 1 1 15 15 1467 80L186EB13 80L186EB8 13 MHz Min Max Min 8 MHz Max Units Notes Parameter OUTPUT CLOCK OUTPUT DELAYS TCHOV2 TCLOV1 3 3 30 25 3 3 35 30 ns ns 1 46 8 146 TCLOV2 3 30 3 35 ns 146 TCHOF 0 30 0 30 ns 1 TCLOF 0 30 0 35 ns 1 34 34 80C186EB 80C188EB 80L186EB 80L188EB AC SPECIFICATIONS AC Characteristics Symbol 80L186EB13 80L186EB8 (Continued) 13 MHz Min Max 8 MHz Min 25 Max ns 19 Units Notes Parameter SYNCHRONOUS INPUTS TCHIS TEST NMI INT4 0 BCLK1 0 T1 0IN READY CTS1 0 P2 6 P2 7 TEST NMI INT4 0 T1 0IN BCLK1 0 READY CTS1 0 AD15 0 (AD7 0) READY READY AD15 0 (AD7 0) HOLD HOLD 20 TCHIH TCLIS TCLIH TCLIS TCLIH 3 20 3 20 3 3 25 3 25 3 ns ns ns ns ns 19 1 10 1 10 19 19 NOTES 1 See AC Timing Waveforms for waveforms and definition 2 Measured at VIH for high time VIL for low time 3 Only required to guarantee ICC Maximum limits are bounded by TC TCH and TCL 4 Specified for a 50 pF load see Figure 13 for capacitive derating information 5 Specified for a 50 pF load see Figure 14 for rise and fall times outside 50 pF 6 See Figure 14 for rise and fall times 7 TCHOV1 applies to BHE (RFSH) LOCK and A19 16 only after a HOLD release 8 TCHOV2 applies to RD and WR only after a HOLD release 9 Setup and Hold are required to guarantee recognition 10 Setup and Hold are required for proper operation 35 35 80C186EB 80C188EB 80L186EB 80L188EB AC SPECIFICATIONS (Continued) Relative Timings (80C186EB25 Symbol RELATIVE TIMINGS TLHLL TAVLL TPLLL TLLAX TLLWL TLLRL TWHLH TAFRL TRLRH TWLWH TRHAV TWHDX TWHPH TRHPH TPHPL TOVRH TRHOX ALE Rising to ALE Falling Address Valid to ALE Falling Chip Selects Valid to ALE Falling Address Hold from ALE Falling ALE Falling to WR Falling ALE Falling to RD Falling WR Rising to ALE Rising Address Float to RD Falling RD Falling to RD Rising WR Falling to WR Rising RD Rising to Address Active Output Data Hold after WR Rising WR Rising to Chip Select Rising RD Rising to Chip Select Rising CS Inactive to CS Active ONCE Active to RESIN Rising ONCE Hold from RESIN Rising T b 15 T b 10 T b 10 T b 10 T b 15 T b 15 T b 10 0 (2 T) b 5 (2 T) b 5 T b 15 T b 15 T b 10 T b 10 T b 10 T T ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 1 1 1 3 3 2 2 1 1 1 1 20 13 80L186EB16 13 8) Min Max Units Notes Parameter NOTES 1 Assumes equal loading on both pins 2 Can be extended using wait states 3 Not tested 36 36 80C186EB 80C188EB 80L186EB 80L188EB AC SPECIFICATIONS (Continued) Serial Port Mode 0 Timings (80C186EB25 Symbol TXLXL TXLXH TXLXH TXHXL TXHXL TQVXH TQVXH TXHQX TXHQX TXHQZ TDVXH TXHDX TXD Clock Period TXD Clock Low to Clock High (n l 1) TXD Clock Low to Clock High (n e 1) TXD Clock High to Clock Low (n l 1) TXD Clock High to Clock Low (n e 1) RXD Output Data Setup to TXD Clock High (n l 1) RXD Output Data Setup to TXD Clock High (n e 1) RXD Output Data Hold after TXD Clock High (n l 1) RXD Output Data Hold after TXD Clock High (n e 1) RXD Output Data Float after Last TXD Clock High RXD Input Data Setup to TXD Clock High RXD Input Data Hold after TXD Clock High T a 20 0 Parameter 20 13 80L186EB16 13 8) Min T (n a 1) 2T b 35 T b 35 2T a 35 T a 35 Max Unit Notes ns ns ns ns ns ns ns ns ns T a 20 ns ns ns 12 1 1 12 1 12 1 1 1 1 1 1 (n b 1) T b 35 (n b 1) T a 35 T b 35 (n b 1) T b 35 T b 35 2T b 35 T b 35 T a 35 NOTES 1 See Figure 12 for waveforms 2 n is the value of the BxCMP register ignoring the ICLK Bit (i e ICLK e 0) 37 37 80C186EB 80C188EB 80L186EB 80L188EB AC TEST CONDITIONS The AC specifications are tested with the 50 pF load shown in Figure 7 See the Derating Curves section to see how timings vary with load capacitance Specifications are measured at the VCC 2 crossing point unless otherwise specified See AC Timing Waveforms for AC specification definitions test pins and illustrations CL e 50 pF for all signals 272433 - 8 Figure 7 AC Test Load AC TIMING WAVEFORMS 272433 - 9 Figure 8 Input and Output Clock Waveform 38 38 80C186EB 80C188EB 80L186EB 80L188EB 272433 - 10 NOTE 20% VCC k Float k 80% VCC Figure 9 Output Delay and Float Waveform 272433 - 11 Figure 10 Input Setup and Hold 39 39 80C186EB 80C188EB 80L186EB 80L188EB 272433 - 12 NOTE Pin names in parentheses apply to 80C188EB 80L188EB Figure 11 Relative Signal Waveform 272433 - 13 Figure 12 Serial Port Mode 0 Waveform 40 40 80C186EB 80C188EB 80L186EB 80L188EB DERATING CURVES TYPICAL OUTPUT DELAY VARIATIONS VERSUS LOAD CAPACITANCE 272433 - 14 Figure 13 TYPICAL RISE AND FALL VARIATIONS VERSUS LOAD CAPACITANCE 272433 - 15 Figure 14 41 41 80C186EB 80C188EB 80L186EB 80L188EB circuit) The RESIN pin is designed to operate correctly using an RC reset circuit but the designer must ensure that the ramp time for VCC is not so long that RESIN is never really sampled at a logic low level when VCC reaches minimum operating conditions Figure 16 shows the timing sequence when RESIN is applied after VCC is stable and the device has been operating Note that a reset will terminate all activity and return the processor to a known operating state Any bus operation that is in progress at the time RESIN is asserted will terminate immediately (note that most control signals will be driven to their inactive state first before floating) While RESIN is active bus signals LOCK A19 ONCE and A18 16 are configured as inputs and weakly held high by internal pullup transistors Only 19 ONCE can be overdriven to a low and is used to enable ONCE Mode Forcing LOCK or A18 16 low at any time while RESIN is low is prohibited and will cause unspecified device operation RESET The processor will perform a reset operation any time the RESIN pin active The RESIN pin is actually synchronized before it is presented internally which means that the clock must be operating before a reset can take effect From a power-on state RESIN must be held active (low) in order to guarantee correct initialization of the processor Failure to provide RESIN while the device is powering up will result in unspecified operation of the device Figure 14 shows the correct reset sequence when first applying power to the processor An external clock connected to CLKIN must not exceed the VCC threshold being applied to the processor This is normally not a problem if the clock driver is supplied with the same VCC that supplies the processor When attaching a crystal to the device RESIN must remain active until both VCC and CLKOUT are stable (the length of time is application specific and depends on the startup characteristics of the crystal 42 42 Figure 15 Cold Reset Waveforms 272433- 16 80C186EB 80C188EB 80L186EB 80L188EB NOTE CLKOUT synchronization occurs on the rising edge of RESIN If RESIN is sampled high while CLKOUT is high (solid line) then CLKOUT will remain low for two CLKIN periods If RESIN is sampled high while CLKOUT is low (dashed line) then CLKOUT will not be affected Pin names in parentheses apply to 80C188EB 80L188EB 43 43 44 272433- 17 80C186EB 80C188EB 80L186EB 80L188EB Figure 16 Warm Reset Waveforms NOTE CLKOUT synchronization occurs on the rising edge of RESIN If RESIN is sampled high while CLKOUT is high (solid line) then CLKOUT will remain low for two CLKIN periods If RESIN is sampled high while CLKOUT is low (dashed line) then CLKOUT will not be affected Pin names in parentheses apply to 80C188EB 80L188EB 44 80C186EB 80C188EB 80L186EB 80L188EB bus signals to CLKOUT These figures along with the information present in AC Specifications allow the user to determine all the critical timing analysis needed for a given application BUS CYCLE WAVEFORMS Figures 17 through 23 present the various bus cycles that are generated by the processor What is shown in the figure is the relationship of the various 272433 - 18 NOTE Pin names in parentheses apply to 80C188EB 80L188EB Figure 17 Read Fetch and Refresh Cycle Waveforms 45 45 80C186EB 80C188EB 80L186EB 80L188EB 272433 - 19 NOTE Pin names in parentheses apply to 80C188EB 80L188EB Figure 18 Write Cycle Waveforms 46 46 80C186EB 80C188EB 80L186EB 80L188EB 272433 - 20 NOTE The address driven is typically the location of the next instruction prefetch Under a majority of instruction sequences the AD15 0 (AD7 0) bus will float while the A19 16 (A19 8) bus remains driven and all bus control signals are driven to their inactive state Pin names in parentheses apply to 80C188EB 80L188EB Figure 19 Halt Cycle Waveforms 47 47 80C186EB 80C188EB 80L186EB 80L188EB 272433 - 21 NOTE Pin names in parentheses apply to 80C188EB 80L188EB Figure 20 Interrupt Acknowledge Cycle Waveform 48 48 80C186EB 80C188EB 80L186EB 80L188EB 272433 - 22 NOTE Pin names in parentheses apply to 80C188EB 80L188EB Figure 21 HOLD HLDA Waveforms 49 49 80C186EB 80C188EB 80L186EB 80L188EB 272433 - 23 NOTES 1 READY must be low by either edge to cause a wait state 2 Lighter lines indicate READ cycles darker lines indicate WRITE cycles Pin names in parentheses apply to 80C188EB 80L188EB Figure 22 Refresh during Hold Acknowledge 50 50 80C186EB 80C188EB 80L186EB 80L188EB 272433 - 24 NOTES 1 READY must be low by either edge to cause a wait state 2 Lighter lines indicate READ cycles darker lines indicate WRITE cycles Pin names in parentheses apply to 80C188EB 80L188EB Figure 23 Ready Waveforms 51 51 80C186EB 80C188EB 80L186EB 80L188EB All instructions which involve memory accesses can require one or two additional clocks above the minimum timings shown due to the asynchronous handshake between the bus interface unit (BIU) and execution unit With a 16-bit BIU the 80C186EB has sufficient bus performance to ensure that an adequate number of prefetched bytes will reside in the queue (6 bytes) most of the time Therefore actual program execution time will not be substantially greater than that derived from adding the instruction timings shown The 80C188EB 8-bit BIU is limited in its performance relative to the execution unit A sufficient number of prefetched bytes may not reside in the prefetch queue (4 bytes) much of the time Therefore actual program execution time will be substantially greater than that derived from adding the instruction timings shown EXECUTION TIMINGS A determination of program execution timing must consider the bus cycles necessary to prefetch instructions as well as the number of execution unit cycles necessary to execute instructions The following instruction timings represent the minimum execution time in clock cycles for each instruction The timings given are based on the following assumptions The opcode along with any data or displacement required for execution of a particular instruction has been prefetched and resides in the queue at the time it is needed No wait states or bus HOLDs occur All word-data is located on even-address boundaries (80C186EB only) All jumps and calls include the time required to fetch the opcode of the next instruction at the destination address 52 52 80C186EB 80C188EB 80L186EB 80L188EB INSTRUCTION SET SUMMARY Function DATA TRANSFER MOV e Move Register to Register Memory Register memory to register Immediate to register memory Immediate to register Memory to accumulator Accumulator to memory Register memory to segment register Segment register to register memory PUSH e Push Memory Register Segment register Immediate PUSHA e Push All POP e Pop Memory Register Segment register POPA e Pop All XCHG e Exchange Register memory with register Register with accumulator IN e Input from Fixed port Variable port OUT e Output to Fixed port Variable port XLAT e Translate byte to AL LEA e Load EA to register LDS e Load pointer to DS LES e Load pointer to ES LAHF e Load AH with flags SAHF e Store AH into flags PUSHF e Push flags POPF e Pop flags 1110011w 1110111w 11010111 10001101 11000101 11000100 10011111 10011110 10011100 10011101 mod reg r m mod reg r m mod reg r m (mod i 11) (mod i 11) port 9 7 11 6 18 18 2 3 9 8 9 7 15 6 26 26 2 3 13 12 1110010w 1110110w port 10 8 10 8 1000011w 1 0 0 1 0 reg mod reg r m 4 17 3 4 17 3 10001111 0 1 0 1 1 reg 0 0 0 reg 1 1 1 01100001 (reg i 01) mod 0 0 0 r m 20 10 8 51 24 14 12 83 11111111 0 1 0 1 0 reg 0 0 0 reg 1 1 0 011010s0 01100000 data data if s e 0 mod 1 1 0 r m 16 10 9 10 36 20 14 13 14 68 1000100w 1000101w 1100011w 1 0 1 1 w reg 1010000w 1010001w 10001110 10001100 mod reg r m mod reg r m mod 000 r m data addr-low addr-low mod 0 reg r m mod 0 reg r m data data if w e 1 addr-high addr-high data if w e 1 2 12 29 12 13 34 8 9 29 2 11 2 12 29 12 13 34 8 9 2 13 2 15 8 16-bit 8 16-bit Format 80C186EB Clock Cycles 80C188EB Clock Cycles Comments Shaded areas indicate instructions not available in 8086 8088 microsystems NOTE Clock cycles shown for byte transfers For word operations add 4 clock cycles for all memory transfers 53 53 80C186EB 80C188EB 80L186EB 80L188EB INSTRUCTION SET SUMMARY (Continued) Function DATA TRANSFER (Continued) SEGMENT e Segment Override CS SS DS ES ARITHMETIC ADD e Add Reg memory with register to either Immediate to register memory Immediate to accumulator ADC e Add with carry Reg memory with register to either Immediate to register memory Immediate to accumulator INC e Increment Register memory Register SUB e Subtract Reg memory and register to either Immediate from register memory Immediate from accumulator SBB e Subtract with borrow Reg memory and register to either Immediate from register memory Immediate from accumulator DEC e Decrement Register memory Register CMP e Compare Register memory with register Register with register memory Immediate with register memory Immediate with accumulator NEG e Change sign register memory AAA e ASCII adjust for add DAA e Decimal adjust for add AAS e ASCII adjust for subtract DAS e Decimal adjust for subtract MUL e Multiply (unsigned) Register-Byte Register-Word Memory-Byte Memory-Word 0011101w 0011100w 100000sw 0011110w 1111011w 00110111 00100111 00111111 00101111 1111011w mod 100 r m 26-28 35-37 32-34 41-43 26-28 35-37 32-34 41-43 mod reg r m mod reg r m mod 1 1 1 r m data mod 0 1 1 r m data data if w e 1 data if s w e 01 3 10 3 10 3 10 34 3 10 8 4 7 4 3 10 3 10 3 10 34 3 10 8 4 7 4 8 16-bit 1111111w 0 1 0 0 1 reg mod 0 0 1 r m 3 15 3 3 15 3 000110dw 100000sw 0001110w mod reg r m mod 0 1 1 r m data data data if w e 1 data if s w e 01 3 10 4 16 34 3 10 4 16 34 8 16-bit 001010dw 100000sw 0010110w mod reg r m mod 1 0 1 r m data data data if w e 1 data if s w e 01 3 10 4 16 34 3 10 4 16 34 8 16-bit 1111111w 0 1 0 0 0 reg mod 0 0 0 r m 3 15 3 3 15 3 000100dw 100000sw 0001010w mod reg r m mod 0 1 0 r m data data data if w e 1 data if s w e 01 3 10 4 16 34 3 10 4 16 34 8 16-bit 000000dw 100000sw 0000010w mod reg r m mod 0 0 0 r m data data data if w e 1 data if s w e 01 3 10 4 16 34 3 10 4 16 34 8 16-bit 00101110 00110110 00111110 00100110 2 2 2 2 2 2 2 2 Format 80C186EB Clock Cycles 80C188EB Clock Cycles Comments Shaded areas indicate instructions not available in 8086 8088 microsystems NOTE Clock cycles shown for byte transfers For word operations add 4 clock cycles for all memory transfers 54 54 80C186EB 80C188EB 80L186EB 80L188EB INSTRUCTION SET SUMMARY (Continued) Function ARITHMETIC (Continued) IMUL e Integer multiply (signed) Register-Byte Register-Word Memory-Byte Memory-Word IMUL e Integer Immediate multiply (signed) DIV e Divide (unsigned) Register-Byte Register-Word Memory-Byte Memory-Word IDIV e Integer divide (signed) Register-Byte Register-Word Memory-Byte Memory-Word AAM e ASCII adjust for multiply AAD e ASCII adjust for divide CBW e Convert byte to word CWD e Convert word to double word LOGIC Shift Rotate Instructions Register Memory by 1 Register Memory by CL Register Memory by Count 1101000w 1101001w 1100000w mod TTT r m mod TTT r m mod TTT r m TTT Instruction 000 ROL 001 ROR 010 RCL 011 RCR 1 0 0 SHL SAL 101 SHR 111 SAR AND e And Reg memory and register to either Immediate to register memory Immediate to accumulator TEST e And function to flags no result Register memory and register Immediate data and register memory Immediate data and accumulator OR e Or Reg memory and register to either Immediate to register memory Immediate to accumulator 000010dw 1000000w 0000110w mod reg r m mod 0 0 1 r m data data data if w e 1 data if w e 1 3 10 4 16 34 3 10 4 16 34 8 16-bit 1000010w 1111011w 1010100w mod reg r m mod 0 0 0 r m data data data if w e 1 data if w e 1 3 10 4 10 34 3 10 4 10 34 8 16-bit 001000dw 1000000w 0010010w mod reg r m mod 1 0 0 r m data data data if w e 1 data if w e 1 3 10 4 16 34 3 10 4 16 34 8 16-bit count 2 15 2 15 11010100 11010101 10011000 10011001 00001010 00001010 1111011w mod 1 1 1 r m 44-52 53-61 50-58 59-67 19 15 2 4 44-52 53-61 50-58 59-67 19 15 2 4 011010s1 mod reg r m data data if s e 0 1111011w mod 1 0 1 r m 25-28 34-37 31-34 40-43 22-25 29-32 25-28 34-37 31-34 40-43 22-25 29-32 Format 80C186EB Clock Cycles 80C188EB Clock Cycles Comments 1111011w mod 1 1 0 r m 29 38 35 44 29 38 35 44 5 a n 17 a n 5 a n 17 a n 5 a n 17 a n 5 a n 17 a n Shaded areas indicate instructions not available in 8086 8088 microsystems NOTE Clock cycles shown for byte transfers For word operations add 4 clock cycles for all memory transfers 55 55 80C186EB 80C188EB 80L186EB 80L188EB INSTRUCTION SET SUMMARY (Continued) Function LOGIC (Continued) XOR e Exclusive or Reg memory and register to either Immediate to register memory Immediate to accumulator NOT e Invert register memory STRING MANIPULATION MOVS e Move byte word CMPS e Compare byte word SCAS e Scan byte word LODS e Load byte wd to AL AX STOS e Store byte wd from AL AX INS e Input byte wd from DX port OUTS e Output byte wd to DX port 1010010w 1010011w 1010111w 1010110w 1010101w 0110110w 0110111w 14 22 15 12 10 14 14 14 22 15 12 10 14 14 001100dw 1000000w 0011010w 1111011w mod reg r m mod 1 1 0 r m data mod 0 1 0 r m data data if w e 1 data if w e 1 3 10 4 16 34 3 10 3 10 4 16 34 3 10 8 16-bit Format 80C186EB Clock Cycles 80C188EB Clock Cycles Comments Repeated by count in CX (REP REPE REPZ REPNE REPNZ) MOVS e Move string CMPS e Compare string SCAS e Scan string LODS e Load string STOS e Store string INS e Input string OUTS e Output string CONTROL TRANSFER CALL e Call Direct within segment Register memory indirect within segment Direct intersegment 11101000 11111111 disp-low mod 0 1 0 r m disp-high 15 13 19 19 17 27 11110010 1111001z 1111001z 11110010 11110010 11110010 11110010 1010010w 1010011w 1010111w 1010110w 1010101w 0110110w 0110111w 8 a 8n 5 a 22n 5 a 15n 6 a 11n 6 a 9n 8 a 8n 8 a 8n 8 a 8n 5 a 22n 5 a 15n 6 a 11n 6 a 9n 8 a 8n 8 a 8n 10011010 segment offset segment selector 23 31 Indirect intersegment JMP e Unconditional jump Short long Direct within segment Register memory indirect within segment Direct intersegment 11111111 mod 0 1 1 r m (mod i 11) 38 54 11101011 11101001 11111111 disp-low disp-low mod 1 0 0 r m disp-high 14 14 11 17 14 14 11 21 11101010 segment offset segment selector 14 14 Indirect intersegment 11111111 mod 1 0 1 r m (mod i 11) 26 34 Shaded areas indicate instructions not available in 8086 8088 microsystems NOTE Clock cycles shown for byte transfers For word operations add 4 clock cycles for all memory transfers 56 56 80C186EB 80C188EB 80L186EB 80L188EB INSTRUCTION SET SUMMARY (Continued) Function CONTROL TRANSFER (Continued) RET e Return from CALL Within segment Within seg adding immed to SP Intersegment Intersegment adding immediate to SP JE JZ e Jump on equal zero JL JNGE e Jump on less not greater or equal JLE JNG e Jump on less or equal not greater JB JNAE e Jump on below not above or equal JBE JNA e Jump on below or equal not above JP JPE e Jump on parity parity even JO e Jump on overflow JS e Jump on sign JNE JNZ e Jump on not equal not zero JNL JGE e Jump on not less greater or equal JNLE JG e Jump on not less or equal greater JNB JAE e Jump on not below above or equal JNBE JA e Jump on not below or equal above JNP JPO e Jump on not par par odd JNO e Jump on not overflow JNS e Jump on not sign JCXZ e Jump on CX zero LOOP e Loop CX times LOOPZ LOOPE e Loop while zero equal LOOPNZ LOOPNE e Loop while not zero equal ENTER e Enter Procedure Le0 Le1 Ll1 LEAVE e Leave Procedure INT e Interrupt Type specified Type 3 INTO e Interrupt on overflow 11001101 11001100 11001110 type 47 45 48 4 47 45 48 4 if INT taken if INT not taken 11001001 11000011 11000010 11001011 11001010 01110100 01111100 01111110 01110010 01110110 01111010 01110 000 01111000 01110101 01111101 01111111 01110011 01110111 01111011 01110001 01111001 11100011 11100010 11100001 11100000 11001000 data-low disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp data-low data-high L 15 25 22 a 16(n b 1) 8 19 29 26 a 20(n b 1) 8 data-high data-low data-high 16 18 22 25 4 13 4 13 4 13 4 13 4 13 4 13 4 13 4 13 4 13 4 13 4 13 4 13 4 13 4 13 4 13 4 13 5 15 6 16 6 16 6 16 20 22 30 33 4 13 4 13 4 13 4 13 4 13 4 13 4 13 4 13 4 13 4 13 4 13 4 13 4 13 4 13 4 13 4 13 5 15 6 16 6 16 6 16 LOOP not taken LOOP taken JMP not taken JMP taken Format 80C186EB Clock Cycles 80C188EB Clock Cycles Comments IRET e Interrupt return BOUND e Detect value out of range 11001111 01100010 mod reg r m 28 33-35 28 33-35 Shaded areas indicate instructions not available in 8086 8088 microsystems NOTE Clock cycles shown for byte transfers For word operations add 4 clock cycles for all memory transfers 57 57 80C186EB 80C188EB 80L186EB 80L188EB INSTRUCTION SET SUMMARY (Continued) Function PROCESSOR CONTROL CLC e Clear carry CMC e Complement carry STC e Set carry CLD e Clear direction STD e Set direction CLI e Clear interrupt STI e Set interrupt HLT e Halt WAIT e Wait LOCK e Bus lock prefix NOP e No Operation 11111000 11110101 11111001 11111100 11111101 11111010 11111011 11110100 10011011 11110000 10010000 (TTT LLL are opcode to processor extension) 2 2 2 2 2 2 2 2 6 2 3 2 2 2 2 2 2 2 2 6 2 3 if TEST e 0 Format 80C186EB Clock Cycles 80C188EB Clock Cycles Comments Shaded areas indicate instructions not available in 8086 8088 microsystems NOTE Clock cycles shown for byte transfers For word operations add 4 clock cycles for all memory transfers FOOTNOTES The Effective Address (EA) of the memory operand is computed according to the mod and r m fields if mod e 11 then r m is treated as a REG field if mod e 00 then DISP e 0 disp-low and disphigh are absent if mod e 01 then DISP e disp-low sign-extended to 16-bits disp-high is absent if mod e 10 then DISP e disp-high disp-low e 000 then EA e (BX) a (SI) a DISP if r m e 001 then EA e (BX) a (DI) a DISP if r m e 010 then EA e (BP) a (SI) a DISP if r m e 011 then EA e (BP) a (DI) a DISP if r m e 100 then EA e (SI) a DISP if r m e 101 then EA e (DI) a DISP if r m e 110 then EA e (BP) a DISP if r m e 111 then EA e (BX) a DISP if r m DISP follows 2nd byte of instruction (before data if required) except if mod e 00 and r m e 110 then EA e disp-high disp-low EA calculation time is 4 clock cycles for all modes and is included in the execution times given whenever appropriate Segment Override Prefix 0 0 1 reg 1 1 0 reg is assigned according to the following Segment reg Register 00 ES 01 CS 10 SS 11 DS REG is assigned according to the following table 16-Bit (w e 1) 8-Bit (w e 0) 000 AX 000 AL 001 CX 001 CL 010 DX 010 DL 011 BX 011 BL 100 SP 100 AH 101 BP 101 CH 110 SI 110 DH 111 DI 111 BH The physical addresses of all operands addressed by the BP register are computed using the SS segment register The physical addresses of the destination operands of the string primitive operations (those addressed by the DI register) are computed using the ES segment which may not be overridden 58 58 80C186EB 80C188EB 80L186EB 80L188EB 5 SINT1 will only go active for one clock period when a receive or transmit interrupt is pending (i e it does not remain active until the S1STS register is read) If SINT1 is to be connected to any of the processor interrupt lines (INT0 - INT4) then it must be latched by user logic An 80C186EB 80L186EB with a STEPID value of 0001H or 0002H has the following known errata A device with a STEPID of 0002H can be visually identified by noting the presence of a ``B'' ``C'' ``D'' or ``E'' alpha character next to the FPO number The FPO number location is shown in Figures 4 5 and 6 1 An internal condition with the interrupt controller can cause no acknowledge cycle on the INTA1 line in response to INT1 This errata only occurs when Interrupt 1 is configured in cascade mode and a higher priority interrupt exists This errata will not occur consistantly it is dependent on interrupt timing ERRATA An 80C186EB 80L186EB with a STEPID value of 0001H has the following known errata A device with a STEPID of 0001H can be visually identified by the presence of an ``A'' alpha character next to the FPO number The FPO number location is shown in Figures 4 5 and 6 1 A19 ONCE is not latched by the rising edge of RESIN A19 ONCE must remain active (LOW) at all times to remain in the ONCE Mode Removing A19 ONCE after RESIN is high will return all output pins to a driving state however the 80C186EB will remain in a reset state 2 During interrupt acknowledge (INTA) bus cycles the bus controller will ignore the state of the READY pin if the previous bus cycle ignored the state of the READY pin This errata can only occur if the Chip-Select Unit is being used All active chip-selects must be programmed to use READY (RDY bit must be programmed to a 1) if waitstates are required for INTA bus cycles 3 CLKOUT will transition off the rising edge of CLKIN rather than the falling edge of CLKIN This does not affect any bus timings other than TCD 4 RESIN has a hysterisis of only 130 mV It is recommended that RESIN be driven by a Schmitt triggered device to avoid processor lockup during reset using an RC circuit REVISION HISTORY This data sheet replaces the following data sheets 270803-004 80C186EB 270885-003 80C188EB 270921-003 80L186EB 270920-003 80L188EB 272311-001 SB80C188EB SB80L188EB 272312-001 SB80C186EB SB80L186EB 59 59 |
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